The inventive concept relates to a full-chip design test and evaluation procedure. More particularly, the inventive concept relates to methods and systems detecting metal line failures in a full-chip design.
Generally, a full-chip operates abnormally when defects, such as metal line failures and/or discrete element (e.g., field effect transistors) failures are present in a completed device. Such failures may be caused by electro static discharge (ESD) inadvertently applied to the full-chip during fabrication, packaging, or related handling. In order to prevent damage from ESD, a full-chip may include certain specialized protection circuit(s) that shield discrete elements and/or associated metal lines from ESD. Unfortunately, the provision of these ESD protection circuits increases the overall size of the full-chip (i.e., reduces the overall degree of integration) and slows performance.
Although many approaches have been suggested for detecting failures during various stages of a full-chip design process, only a design rule check has conventionally been applied to identify metal line failures. In a design rule check, metal line failures may be detected by determining whether the widths of metal lines are less than a corresponding design rule. Unfortunately, the accuracy of the design rule check is low and may only be applied over a relatively narrow detection area. Thus, the design rule check is relatively ineffective and inefficient in detecting metal line failures in the full-chip design phase.